Programmable integrated circuit devices are well known in the art. See for example U.S. Pat. No. Re 34,363, whose disclosure is incorporated herein by reference in its entirety. Such devices can be programmed at the factory or in the field. In the case of the latter, they can be referred to as FPGA (Field Programmable Gate Array). Typically, they comprise an array of logic elements, each of which can be programmed to perform a particular logical function. In addition, a plurality of interconnect lines surround the plurality of logic elements. Each of the logic elements may be programmably connected to the plurality of interconnect lines. In addition, the interconnect lines may be programmably routed to supply signals to different logic elements.
Referring to FIG. 1 there is shown a block level diagram of a programmable integrated circuit device 10 of the prior art, as disclosed in U.S. Pat. No. Re 34,363. The device 10 comprises an array of logic elements 12 arranged in a plurality of rows and columns. Each of the logic elements 12 can be programmed to perform a particular logic function, such as AND OR or other logic functions. Each row of logic elements 12 is separated from one another, and each column of logic elements 12 is also separated from one another. Between the separation of the rows of logic elements 12 and the columns of logic elements 12 is a group of interconnect lines 14. The group of interconnect lines 14 comprises a plurality of lines 14. The group of lines 14 pass through a plurality of switches 16, which are also arranged in a plurality of rows and columns. Each of the switches 16 routes the connection of the interconnect lines from rows to columns or vice-versa. The group of interconnect lines 14 are also connected to a plurality of connection boxes 18. Each of the connection boxes 18 connects one or more of the group of interconnect lines 14 to an associated logic element 16.
Each of the logic element 12 has a plurality of input leads, which are connected to the group of interconnect lines 14, through an associated connection box 18. Further, each of the logic element 12 has at least one output lead, which is also connected to the group of interconnect lines 14 through an associated connection box 18. In this manner, the logic function of each logic element 12 can be changed, as well as the routing of the signals to/from each logic element 12 to other logic elements 12 can be changed.
Referring to FIG. 2 there is shown in greater detail a portion of the device 10 shown in FIG. 1. In particular, FIG. 2 shows in greater detail the group of interconnect lines 14 as comprising a plurality of lines 14, connected to a switch 16 and to a connection box 18 and to a logic element 12.
Referring to FIG. 3 there is shown in greater detail a circuit diagram of a common component of a logic element 12 in the nature of a Look-up Table (LUT). Another common component of a logic element is a D-flipflop (not shown). A plurality of input leads 21 is shown, connected to the logic element 12. The input leads 21 are “decoded” by logic gates 22. The resulting signals are used to select one of the memory elements 20 to be programmably connected to output lead 24. As previously discussed, the input leads 21 and the output lead 24 are connected to the group of interconnect lines 14, so that the signals on those input/output leads 21/24 can be routed to other logic elements 12. The set of memory elements 20 are used to configurable the LUT to the desired function. Typically, these memory elements may be SRAM cells or non-volatile cells like Flash or fuses. A logic element 12 may contain one or more LUTs and one or more D-flip-flops.
The problem with the device 10 is that as the scale of integration increases, more and more logic elements 12 can be fabricated on a single integrated circuit die. For example, in 1990, a single programmable logic device may contain hundreds of LUTs, whereas it is possible today to integrate hundreds of thousand LUTs in a single die. As the number of LUTs are placed on a single integrated die increases, the testing of each of the logic elements 12 becomes increasingly time consuming. While it is very probable that not all gates or logic elements 12 will be used, once the device 10 is manufactured, nevertheless, the manufacturer of the device 10 must test each and every gate or logic element 12. Thus, increasingly, testing has become a larger cost portion of the fabrication of the device 10.
More importantly, much of the test time associated with logic elements 12 is the time it takes to write new information into the memory cells 20. For memory cells 20 that have very long write times, such as Flash memory cells, the test time will be proportionally long.
It is, therefore, an object of the present invention to reduce the test time of an integrated circuit device having a plurality of programmable logic elements.